1. Field of the Invention
The present invention relates generally to microprocessors, and more particularly, to systems and methods for a microprocessor to efficiently integrate operations with an on-die co-processor.
2. Description of the Related Art
Microprocessors can often include both a central processing unit (CPU) and a specialty co-processor on one die. The specialty co-processor can perform any type of operation to assist the CPU to rapidly process the required data. FIG. 1A shows an exemplary microprocessor die 100 that includes a CPU 110 and a co-processor 120. The co-processor 120 can be a cryptographic co-processor. The cryptographic processor 120 can be included on the same die 100 as the CPU 110 because a cryptographic operation is a relatively complex and time-consuming process. Therefore having the cryptographic co-processor 120 on the same die 100 with the CPU 110 can allow for faster cryptographic operations as compared to having the cryptographic co-processor external to (e.g., peripheral) the CPU die 100.
FIG. 1B is a flowchart of the method operations 140 for the typical CPU 110 and cryptographic co-processor 120 to process a cryptographic operation request. FIG. 1C is a graphical representation of a time line 180 for processing the same cryptographic operation request. In operation 142, the CPU 110 receives an operation request such as a data packet. In operation 144, the CPU 110 identifies the received request as a crypto operation request. By way of example an IPsec encrypted packet can be received in the CPU 110. Software in the CPU can identify the packet as an IPsec encrypted packet. In operation 146, the CPU sends the IPsec packet to the crypto co-processor 120 to be processed.
Referring now to both FIGS. 1B and 1C, operations 142-144 occur between time T0 and time T1, operation 146 occurs at time T1. Between times T0 and T1, the crypto co-processor 120 is sitting idle (i.e., stalled) waiting for a crypto operation request to be transferred to the crypto co-processor. At time T1, in operation 146, once the crypto operation request is transferred to the crypto co-processor 120, the CPU retrieves and begins processing a subsequent operation request or requests in operation 148.
Between time T1 and time T2, the crypto co-processor 120 processes the crypto operation request such as in operations 150-152. In operation 150, the crypto co-processor 120 identifies the data required to execute the crypto operation. By way of example, a required decryption key may be identified. Unfortunately, the crypto co-processor 120 cannot access the required decryption key because it does not know where the key is located. Further, the crypto co-processor 120 cannot directly access the memory. In operation 152, at time T2, the crypto co-processor 120 sends a request for the identified data to the CPU 110. The crypto co-processor 120 then stalls because processing the single crypto operation request cannot continue until the required decryption key is received by the crypto co-processor.
In operation 154, the CPU 110 interrupts the operation request then currently being processed. Alternatively, the CPU 110 can wait until the then current operation request is completed. In operation 156, the CPU 110 retrieves the identified data (e.g., the decryption key). In operation 158, the CPU 110 provides the identified data to the crypto co-processor 120. Once the identified data is provided to the crypto co-processor 120, the CPU 110 can resume the interrupted operation request or alternatively retrieve a subsequent operation request. If the subsequent operation request is identified as another crypto operation request, the CPU 110 may stall waiting for the crypto co-processor to be available to execute the subsequent crypto operation request.
At time T3, in operations 160 and 162, the crypto co-processor 120 resumes processing the crypto operation request and completes the crypto operation request. By way of example, the crypto co-processor can decrypt the crypto operation request to produce a decryption result.
In operation 164, at time T4, the crypto co-processor 120 notifies the CPU 110 that the current crypto operation request has been completed. The crypto co-processor 120 then stalls until the CPU 110 requests the result of the completed crypto operation request. In operation 166, the CPU 110 interrupts (or alternatively completes) the then current operation request before responding to the completed notice from the crypto co-processor 120 at time T5.
Operations continue in similar theme as subsequent crypto operation requests are received in the CPU 110 and passed to the crypto co-processor 120 for execution. The above-described method operations 142-166 are very inefficient because the crypto co-processor 120 is often stalled waiting for the necessary data to complete a crypto operation request. Further, the constant interruptions of the CPU 110 by the crypto co-processor 120 reduce the efficiency of processing in the CPU. Further still, if the CPU 110 retrieves multiple crypto operation requests in short succession (e.g., before the crypto co-processor 120 has completed the previous crypto operation request), the CPU may stall waiting for the crypto co-processor to become available to execute a subsequent crypto operation request.
In the past, these shortcomings have been addressed in numerous approaches. One approach has been to increase the speed (i.e., frequency) of the data bus (e.g., bandwidth) between the CPU 110 and the crypto co-processor 120. Including both the CPU and crypto co-processor to the same die 100 has also reduced some delay times and increased throughput somewhat. Another approach has been to simply drive the processing speed (e.g., clock speed) of the CPU and crypto co-processor ever faster. However, while each of these approaches failed to address the fundamental problem of an inefficient system and method of communication between the CPU 110 and the crypto co-processor 120. In view of the foregoing, there is a need for a system and method to provide improved communication efficiency between the CPU 110 and the crypto co-processor 120.